1. Field of the Invention
The present invention relates to an image display control method for use in a liquid crystal display apparatus, a plasma display apparatus, an EL (electro-luminescence) display apparatus and the like to display images, and to an image display control apparatus.
2. Prior Art
As conventional techniques regarding an image display control method and an image display control apparatus, a liquid crystal display control method and a liquid crystal display control apparatus will now be described.
FIG. 4 is a schematic block diagram of a conventional liquid crystal display control apparatus as it handles a liquid crystal display (image display) request and a host computer access request. In FIG. 4, denoted at 401 is a host computer, namely, a micro computer unit. Denoted at 402 is a host interface circuit. Denoted at 403 is a memory circuit which stores display data. Denoted at 404 is a line latch circuit which stores one horizontal line-equivalent display data which is used to realize liquid crystal display (image display). Denoted at 405 is a memory select address location which is in response to a host access. Denoted at 406 is a memory line select address location which is in response to an LCD display read access. Denoted at 407 is a display line data transfer signal for an LCD display read access.
As the host computer 401 accesses in order to write display data, pixel data is written at the memory address select location 405 which corresponds to a vertical-direction and a horizontal-direction addresses within the memory circuit 403. Meanwhile, since display data one horizontal line equivalent to needs be transferred to the line latch circuit 404 to realize liquid crystal display (image display), a vertical address corresponding to one horizontal line is selected from among addresses within the memory circuit 403 in accordance with the memory line select address location 406 which is in response to the LCD display read access. The data representing thus selected line is sent to the line latch circuit 404 based on the display line data transfer signal 407.
An access request to the memory circuit 403 from the host computer 401 is in an asynchronous relationship with an access request to the memory circuit 403 from the liquid crystal display apparatus. Hence, while the host computer 401 and the liquid crystal display apparatus both access, the same data address could be selected.
FIG. 5 is a schematic diagram showing an example of a 1-bit structure within a memory circuit and a relationship with a line latch circuit. In FIG. 5, denoted at 501 is a 1-bit memory. Denoted at 502 is an initialization circuit. Denoted at 503 is a line latch circuit. Denoted at 504 is a line select signal. Denoted at 505 is a memory output. Denoted at 506 is an output from the initialization circuit 502. Denoted at 507 is a display read bus.
The 1-bit memory 501 within the memory circuit is formed by a P-channel or N-channel transistor for a small size. Within the memory circuit, a display read operation for a line selected by the line select signal 504 is as follows. That is, the display read bus 507 is initialized in response to the initialization output 506 from the initialization circuit 502, the memory output 505 from the 1-bit memory 501 is then outputted to the display read bus 507, and the line latch circuit 503 receives OR of the initialization output 506 and the memory output 505. When a P-channel transistor is used for example, the memory output 505, namely, read data is in a high-level state or high-impedance state, and therefore, the initialization circuit 502 reads the L-level.
FIGS. 6 and 7 are timing charts which show an example that there is no contention between an access request from the host computer and an access request for liquid crystal display (image display) and an example that there is such a contention.
Shown in FIG. 6 is a normal state that there is no contention between a host computer access and a display read access. In FIG. 6, a high-level pulse T611 occurs in a display read signal 611, at which time a value T612 (00—1111) of memory data 612 changes to a value T613 (00—1111) of a display read data output 613 from the memory circuit. Meanwhile, the pulse T611 of the display read signal 611 makes the initialization circuit execute initialization, and the state of a display read bus 614 therefore becomes an initialized state T614.
After this, because of the value T613 of the display read data output 613, the state of the display read bus 614 becomes a value T615 (00—1111). As a high-level pulse T616 occurs in a display line data transfer signal 616, a line latch output 617 becomes a value T617 (00—1111).
FIG. 7 shows a state that there arises a contention between a host computer access and a display read access. As shown in FIG. 7, a high-level pulse T621 occurs in a display read signal 621, at which time a value T622 (00—1111) of memory data 622 changes to a value T623 (00—1111) of a display read data output 623 from the memory circuit. Meanwhile, the pulse T621 of the display read signal 621 makes the initialization circuit execute initialization, and the state of a display read bus 624 therefore becomes an initialized state T624.
After this, because of the value T623 of the display read data output 623, the state of the display read bus 624 becomes a value T625 (00—1111).
When the memory data 622 changes to a value T626 (00—1111) owing to a host computer access during a contending data display period T631 which is influenced by the access contention, the display read data output 623 from the memory circuit becomes a value T627 (00—1111). In consequence, the state of a display read bus 624 undesirably becomes a value T628 (11—1111) which is OR of the value T625 (00—1111) and the value T627 (00—1111). As a high-level pulse T629 occurs in a display line data transfer signal 629, a line latch output 630 undesirably becomes a value T630 (11—1111) which is influenced by the access contention.
The following may be a method of avoiding an access contention in a situation that an access to the memory circuit from the host computer is in an asynchronous relationship with a display read access to the memory circuit from the liquid crystal display apparatus. In other words, when the host computer sends an access request while the liquid crystal display apparatus sends an LCD access request, an arbitration circuit may provide arbitration and RAM accessing responding to either one of the access requests may be initiated. At this stage, the arbitration circuit permits initiation of accessing under a condition that pre-charging of the RAM has finished. When there is a contention between a host access request and an LCD access request, the host access request is always given a priority (See PCT Publication in Japan 2000-003381 (page 1, FIG. 2).). The arbitration circuit may be the one described in Japanese Patent Application Laid-Open Gazette No. H10-105505 (pages 6 to 8, FIG. 5), for instance.
However, during the arbitration in the conventional structure described above, when a display read access from the liquid crystal display apparatus is earlier than a write access from the host computer for example, displaying will be provided before the arbitration circuit stops display read. There thus remains a problem that the contending data will be displayed.
In addition, when a contention with a host access arises once again upon resumption of an LCD access in response to an operation of the arbitration circuit, the arbitration will continue. This is a problem that displaying will not be provided indefinitely or that the complex arbitration circuit gives rise to malfunction.